Makefile: compile .o from .c files -

i not have experience makefiles, answer may obvious. however, not able find looking in gnu make manual or elsewhere on stackoverflow. have run issue few times, have made example project demonstrate it.

i have directories:

• src/ .c files
• build/ library being built
• obj/ .o files (one being compiled different project)

what looks like:

$ ls -l total 0 drwxrwxr-x+ 1 sam none 0 jan  5 15:43 build drwxrwxr-x+ 1 sam none 0 jan  5 15:43 obj drwxrwxr-x+ 1 sam none 0 jan  5 15:42 src 

my makefile:

cc=gcc cflags=-wall  sources=$(wildcard src/*.c) source_objects=$(patsubst src/%.c,obj/%.o,$(sources))  objects=$(wildcard obj/*.o)  hashsrc=/cbib/libhash/src/hash.c  target=target.a  all: $(target)  $(target): $(objects)     ar rcs $@ $^  obj/%.o: src/%.c     $(cc) -o $@ $^ $(cflags)  obj/hash.o: $(hashsrc)     $(cc) -o $@ $^ $(cflags) 

the rule

obj/%.o: src/%.c 

catches .o files in obj/ directory. want catch files listed in source_objects, , compile them corresponding files in src/ directory. how this?

objects=$(wildcard obj/*.o) empty, because wildcard returns existing files. should depend on $(source_objects) in $(target).

when dealing multiple input sources can narrow down selection:

# dest files        dest pattern  source pattern $(source_objects):  obj/%.o:      src/%.c     $(cc) -o $@ $^ $(cflags) 

there further minor errors (or shortcomings) in makefile. e.g. creates directory obj/? can depend on directory like:

obj/%.o: | obj/  obj/:     mkdir -p $@