memory - SP605 Spartan 6 DDR3 addressing -

the following post quite long, since have had trouble making sp605 board interact ddr3 on month now, useful others in same situation find myself in. pretty it's simple configuration or conceptual error, more happy have resolved soon.

=== scenario ===

i have created usb-uart interface communicate fpga , control ddr3. using ip generator in ise, generated mig wrapper , designed memory interface controller. however, have referenced manuals ug388 , ug416, have not been able have ddr3 behave expected.

=== problem statement ===

playing around burst lengths write , read commands, able data ddr3, yet addressing scheme not seem correct data duplicated in addresses 0 , 1, 2 , 3, 4 , 5, , forth. also, whenever write address 0, example, nothing changes. then, when write address 1, both addresses 0 , 1 updated data value sent. seems "losing" half of memory space due coupled effect.

=== ddr3 ip configuration ===

the setup ddr3 using ip generator – considering sp605 board scenario – listed below. in sum, activated ddr3 bank 3 , configured port0 32-bit bidirectional.

memory selection:

• enable axi interface: unchecked

• use extended mcb performance range: unchecked

• memory type bank 3: ddr3 sdram

• memory type bank 1: none

options c3 – ddr3 sdram

• frequency: 400 mhz

• memory part: mtj41j64m16xx-187e

memory options c3 – ddr3 sdram

• output driver impedance control: rzq/6

• rtt (nominal) – odt: rzq/4

• auto self refresh: enabled

port configuration c3 – ddr3 sdram

• two 32-bit bi-directional , 4 32-bit unidirectional ports

• port0: checked

• port1: unchecked

• port2: unchecked

• port3: unchecked

• port4: unchecked

• port5: unchecked

• memory address mapping selection: row-bank-column

fpga options c3 – ddr3 sdram

• memory interface pin termination: calibrated input termination

• select rzq pin location: r7

• select zio pin location: w4

• debug signals memory controller: disable

• system clock: differential

=== data structure ===

from matlab, send in 64-bit command should write or read ddr3 based on address , data provided in command.

wire [00:00] cmd_instruction = usb_data[63:63];         // ‘0’ = write; ‘1’ = read wire [27:00] cmd_address = usb_data[62:37];             // 26-bit address wire [31:00] cmd_data = usb_data[31:00];                // 32-bit data 

in ug388, following can extracted:

page 20: address 26 bits wide.

c_mem_addr_width = 13 c_mem_bankaddr_width = 3 c_mem_num_col_bits = 10 c_p0_data_port_size = 32  // 32-bit data ports c_p0_mask_size = 4        // 4 bytes = 32 bits (1 mask bit = 1 entire data byte) 

pages 26-27: command data structure.

• px_cmd_addr[29:0]: 30-bit address, last 2 bits should = “00” since every word (32 bits) formed 4 bytes.

• px_cmd_bl[5:0]: burst length of 1 obtained setting signal 0.

• px_cmd_instr[2:0]: command instructions used write=”000” , read=”001”.

page 28: write data structure.

• px_wr_mask[px_masksize-1:0]: 4-bit mask set “0000” 4 bytes written memory.

=== signal assignments ===

using information, assigned signals in following manner:

assign p0_mcb_cmd_instr = {2'b00, cmd_instruction}; assign p0_mcb_cmd_addr = {2’d0, cmd_address, 2'd0}; assign p0_mcb_cmd_bl = 6'd0; assign p0_mcb_wr_data = cmd_data; assign p0_mcb_wr_mask = 4'd0;  localparam c3_mem_burst_len = 8;  

=== conclusions ===

based on configuration, know expected behavior of controller should be? if additional information necessary clarification, please let me know.

thanks lot, bruno.